The present invention relates a semiconductor integrated circuit device and manufacturing techniques therefor, and more particularly to techniques which are effectively applied to a semiconductor integrated circuit device having a DRAM (Dynamic RAM). It is first noted that in the following description, an n-channel MOS FET is abbreviated as "nMOS" and a p-channel MOS FET as "pMOS".
The number of bits in DRAMs has been more and more increased. This is because the DRAM has characteristics suitable for enhancing the integration degree: for example, the cell structure of a DRAM is rather simple among all kinds of semiconductor memories; the pattern design is regularly made so that a large scaled design is possible for the DRAM; the cell area can be made small; and so on.
With further progressive increases in the number of bits in DRAMs, an important problem to be solved is how to ensure a sufficient storage capacitance of capacitors constituting memory cells in the DRAM. This problem is caused mainly by the use of a lower voltage in the DRAM, which lower voltage is promoted in view of reduction in an area occupied by each memory cell, and in order to ensure the reliability of the device.
FIG. 74 shows an example of a partial plan view of a conventional memory cell array. A memory cell array 50 includes word line conductors (identified by shaded areas) 51 extending in the vertical direction, when viewed on FIG. 74, which are repetitively arranged along the horizontal direction on FIG. 74.
Bit line conductors 52 extending orthogonal or perpendicular to the word line conductors 51 are repetitively arranged in the vertical direction as viewed in FIG. 74. On both sides of each bit line connector 54 connecting a bit line conductor 52 and a MOS FET (hereinafter simply abbreviated as "MOS") 53, memory cells 55 are arranged. Each of the memory cells 55 is constituted of the MOS 53 and a capacitor 56. The capacitor 56 includes a node electrode 58 provided separately for each individual memory cell, a plate electrode 59 provided in common to plural memory cells and a dielectric film sandwiched therebetween.
Conventionally, the memory cells 55 are positionally shifted by one-half of a periodic pattern alternately to the left and to the right on FIG. 74 each time the bit line conductor 52 is repetitively arranged. For this reason, the capacitors 56 in the plurality of memory cells 55 are linearly aligned in the vertical direction on FIG. 74.
The following references disclose respective proposals of layouts of memory cells:
a. JP-A-5-13673 (laid open on Jan. 22, 1993); PA1 b. JP-A-3-72675 (laid open on Mar. 27, 1991); and PA1 c. JP-A-6-5811 (laid open on Jan. 14, 1994). PA1 d. Extended Abstract of the 21st Conference on Solid State Devices and Materials, Tokyo, 1989, pp. 105-108; PA1 e. JP-A-56-87340 (laid open on Jul. 15, 1981); PA1 f. JP-A-62-298161 (laid open on Dec. 25, 1987) corresponding to U.S. Pat. No. 5,116,775; and PA1 g. U.S. Pat. No. 3,860,454 (issued on Jan. 14, 1975). PA1 h. Shaw, et al., "A Capacitor-Over-Bit Line (COB) Cell With a Hemispherical-Grain Storage Node for 64 Mb DRAMs", IEDM '90, pp. 655-658; and PA1 i. JP-A-5-259405 (laid open on Oct. 8, 1993). PA1 j. JP-A-5-226583 (laid open on Sep. 3, 1993); PA1 k. JP-A-6-77428 (laid open on Mar. 18, 1994); and PA1 l. JP-A-5-82750 (laid open on Apr. 1, 1993). PA1 adjacent two memory cells for each bit line conductor form a memory cell pair unit structure, in which each of the memory cell pair unit structures includes a first information storage capacitor, a first switching transistor, a second switching transistor and a second information storage capacitor arranged in the described order under one of the bit line conductors in a lengthwise direction of the bit line conductors, each of the transistors having a pair of semiconductor regions formed in the substrate and a control electrode formed between the pair of semiconductor regions over the substrate, an electric current being caused to flow between the pair of semiconductor regions when the transistor is conductive responsive to a control signal applied to the control electrode, one of the pair of semiconductor regions of the first transistor and one of the pair of semiconductor regions of the second transistor being united at their boundary into a single region and being connected to one of the bit line conductors via a bit line connection conductor, the gate electrodes of the first and second transistors being connected to word line conductors adjacent to each other, respectively, the others of the pair of semiconductor regions of the first and second transistors being connected to the first and second information storage capacitors, respectively, the first information storage capacitor and the first switching transistor forming one of the adjacent two memory cells, the second information storage capacitor and the second switching transistor forming the other of the adjacent two memory cells; and PA1 a series of memory cell pair unit structures formed under one bit line conductor is positionally shifted with respect to a series of memory cell pair unit structures formed under adjacent first and second bit line conductors on opposite sides of the one bit line conductor, respectively, in a direction parallel with the bit lines such that a second information storage capacitor of a memory cell pair unit structure formed under the adjacent first bit line conductor and a first information storage capacitor of a memory cell pair unit structure formed under the adjacent second bit line conductor are located adjacent to a bit line connection conductor of a memory cell pair unit structure formed under the one bit line conductor, as viewed in a direction perpendicular to the substrate. PA1 (a) depositing a low-resistance polysilicon film, after forming first contact holes each for exposing one semiconductor region of the transistor through a first insulating film covering the DRAM cells and the transistors, in such a degree that the top surface thereof is made substantially planar; PA1 (b) etching back an upper portion of the low-resistance polysilicon film so as to leave the low-resistance polysilicon film only in the first contact holes; PA1 (c) diffusing predetermined impurities from the low-resistance polysilicon film filled in the first contact holes to the one semiconductor region; PA1 (d) forming second contact holes reaching elements in the peripheral circuit region through the first insulating film, and thereafter depositing a predetermined metal film over the semiconductor substrate; and PA1 (e) patterning the metal film to form bit line conductors electrically connected to the low-resistance polysilicon film filled in the first contact holes to constitute memory circuits and first level wiring conductors electrically connected to the elements to constitute peripheral circuits. PA1 (a) depositing a first conductive film for forming a first fin for each of the fin-shaped capacitors, after forming contact holes each for exposing one semiconductor region of the transistor through an insulating film for covering the transistor; PA1 (b) etching back an upper portion of the first conductive film to flatten the top surface thereof; and PA1 (c) forming second and subsequent fins for each of the capacitors on the flattened top surface of the first conductive film. PA1 (a) depositing, after forming a protective insulating film on a first insulating film covering the transistors, a second insulating film on the protective insulating film, an etching rate of the second insulating film being different from that of the protective insulating film; PA1 (b) forming a first conductive film for forming a first fin for each of the capacitors of the stacked fin structure in such a degree that the top surface thereof is flattened, after forming contact holes each for exposing one semiconductor region of the transistors through the first insulating film, the second insulating film and the protective insulating film; PA1 (c) etching back the top surface of the first conductive film to flatten the top surface thereof; PA1 (d) depositing a second conductive film for forming a second and subsequent fins for each of the capacitors on the flattened top surface of the first conductive film with a third insulating film being interposed therebetween; and PA1 (e) removing the third insulating film interposed between the second insulating film and the fins with the protective insulating film being used as an etching stopper layer, after the first conductive film and the second conductive film are patterned.
Formation of channel stoppers by ion implantation through field insulating films formed by the LOCOS technique is shown, for example, in the following references:
Examples of structures for electrical connection between bit line conductors and switching transistors of memory cells are disclosed in the following references:
Further, examples of structures of an information storage capacitor of a memory cell are disclosed in the following references: